1. Field of the Present Invention
The present invention relates to a pulse width modulation (PWM) control and, more particularly, to PWM control which is used in a meter control.
2. Description of the Related Art
In each of the meters on the dash board of an automobile, a value pointed by a needle of the meter changes in accordance with change in vehicle speed, rotational speed of an engine, or the like. The Pulse Width Modulation (PWM) control is typically used to change the position of the needle of each meter in accordance with the change in vehicle speed, rotational speed of an engine, or the like.
FIG. 1 shows a block diagram illustrating the structure of a conventional meter control circuit, as in Japanese Laid Open Patent Application (JP-A-Heisei 3-228102), for example. Referring to FIG. 1, a set value is written from a bus 210 into a master compare register 203 in response to generation of a write request signal. When a transfer control signal 209s from a transfer control circuit 204 is in a transfer permission state, the set value is transferred from the master compare register 203 to the slave compare register 202 in synchronous with the overflow signal 206s of the free run counter 201. A coincidence signal 207s is generated when a count value of a free run counter 201 and a set value on a slave compare register 202 coincide. Also, the overflow signal 206s is generated when the free run counter 201 overflows. A PWM output signal 208s is formed from the coincidence signal 207s and the overflow signal 206s.
However, when the overflow signal 206s is generated during the writing operation of the set value into the master compare register 203 through the bus 210, there is a possibility that the set value is transferred to the slave compare register 202 through the master compare register 203 on the way of writing operation. For this reason, the transfer control circuit 204 is provided to control the transfer of the set value from the master compare register 203 to the slave compare register 202. Thus, an erroneous operation can be prevented even in the case where the overflow signal 206s is generated during the rewriting operation on the master compare register 203, as mentioned above.
To prevent the erroneous operation in the above circuit structure, the following transfer control is performed. That is, when the transfer control signal 209s is in a transfer permission state, the transfer control circuit 204 permits the set value to be transferred from the master compare register 203 to the slave compare register 202 in synchronous with the overflow signal 206s from the free run counter 201, as shown by an arrow A. On the contrary, the transfer control circuit 204 inhibits the set value from being transferred from the bus 210 to the master compare register 203, as shown by an arrow B.
On the other hand, when the transfer control signal 209s is in a transfer inhibition state, the transfer control circuit 204 inhibits the set value from being transferred from the master compare register 203 to the slave compare register 202, even if the overflow signal 206s is generated from the free run counter 201. On the contrary, the transfer control circuit 204 permits the set value to be written into the master compare register 203 through the bus 210, as shown by the arrow B.
FIG. 2 shows a control flow in the conventional circuit after the write request signal is generated. In the conventional circuit, when a write request signal is generated in a step S32, the transfer control circuit 204 is set in the transfer inhibition state in a software manner in a step S34. Then, the set value is written by a CPU (not shown) to the master compare register 203 through the bus 210 in a step S36. Subsequently, the transfer control circuit is set in the transfer permission state in a software manner in a step S38. The above steps are repeated until the overflow signal is generated. When the overflow signal 206s is generated from the free run counter 201, the transfer of the set value from the master compare register 203 to the slave compare register 202 is executed in synchronous with the overflow signal in a step S40.
FIG. 3 shows a relation between the overflow signals 206s of the free run counter 201 and the write request signals to the master compare register 203. As shown in FIG. 3, the many write request signals are generated between an overflow signal 206s and the next overflow signal 206s from the free run counter 201. In this case, The CPU sets the transfer control circuit 204 into the transfer inhibition state each time the write request signal is generated. Then, the CPU writes a set value into the master compare register 203. Thereafter, the CPU sets the transfer control circuit 204 to the transfer permission state. This processing is repeated each time the write request signal is generated for a time period between the overflow signal 206s and the next overflow signal 206s.
As a consequence, however, only the set value written into the master compare register 203 just before the generation of the overflow signal 206s is transferred to the slave compare register 202. Thereby, the latest set value is reflected to the PWM output signal 208s. That is, the set values other than the value written into the master compare register 203 just before the generation of the overflow signal 206s are not used.
Since the transfer of the set value shown by the arrow A is controlled by the transfer control circuit 204, the set value is not transferred from the master compare register 203 to the slave compare register 202 even when the overflow signal 206s is generated during the writing operation of the value into the master compare register 203. Therefore, there would be a case that the value of the slave compare register 203 is not updated. In this manner, the PWM output signal cannot be not changed in spite that targets to be pointed by the meters such as vehicle speed, rotational speed of the engine, etc. are changed.
As described above, there are the following problems in the conventional circuit.
As a first problem, the CPU performs useless processing. In the conventional circuit, the set value is written to the master compare register through the bus by the number of times of generation of the write request for the time period from a overflow signal and the next overflow signal from the free run counter. However, even if the value is written many times from the bus to the master compare register, only the latest value which has been finally written among them is eventually transferred as a valid value to the slave compare register. Therefore, any values overwritten on the master compare register other than the latest value are not reflected to the PWM output. As a result, the CPU performs the useless processing.
As a second problem, the transfer control circuit 204 controls the transfer of the set value from the master compare register to the slave compare register. Therefore, there would be a case that the set value on the slave compare register is not updated in dependence on a timing. In other words, when the overflow signal is generated from the free run counter during the writing operation of the set value into the master compare register, the transfer of the set value from the master compare register to the slave compare register is not permitted, since the value is being written into the master compare register. Therefore, the set value is not transferred from the master compare register to the slave compare register. Thus, the set value on the slave compare register is not updated and the PWM output signal does not change.